Integrated circuit (IC) designs may have circuitry with different components that may operate and produce signals in accordance to different timing domains. For example, an IC may have components and signals that operate according to a particular clock domain while also having other components and signals that operate according to a different clock domain. In order for signals originating from one clock domain of the IC to traverse into another asynchronous clock domain of the IC, signal synchronization may be required.
Signal synchronization may utilize synchronizing flip-flops (FF's) to take an input signal (e.g., a data signal) of a first clock domain that is asynchronous to a second clock domain and generate corresponding signals that are synchronized to the second clock domain. For example, current methods for synchronization may utilize multiple stages of specially designed synchronizing flip-flops in series to achieve synchronization. However, such methods present significant design limitations. For example, there may be cases where the frequency of the receiving clock domain increases substantially. Synchronizing a signal to the higher frequency clock domain may require the use of increasing numbers of FF stages to enable adequate synchronization. Additional FF stages may also be necessary in order to meet a given Mean Time Between Failures (MTBF) signal parameter for the design. This use of ever increasing FF stages leads to increases in latency of the synchronized signals and associated data transfers which often results in diminished system performance.
Signal synchronization from one clock domain to another clock domain may also present other challenges that current synchronization methods may not address. For example, because clocks of two differing timing domains have no guaranteed relationship to one another, input signals (e.g., data signals) to be synchronized may change value (e.g., logic value) at anytime with respect to the receiving clock domain (e.g., the clock the signal is to be synchronized to). Such value changes may even occur within timing constraints of the design, such as within the window between setup and hold timing constraints. When such setup and hold timing constraints are violated by the changes in values of the input signal, the signals inside the receiving flip-flop stages may require extra time to resolve these changes and latch a stable state of the incoming data. The lack of state stability of the signal due to these changes may lead to logic failures within receiving flip-flop stages of the receiving clock domain. Current synchronization methods are limited in addressing state stability issues associated with signals that undergo a synchronization process.
Consequently, there is the need for synchronization circuitry that can provide synchronized signals with reduced latencies for clock domains with increased frequencies in a manner that utilizes minimal circuit stages. Furthermore, there is a need that such synchronization circuitry may resolve any state stability issues associated with signals to be synchronized with asynchronous clock domains in order to provide reliable stability for data states for signals undergoing signal synchronization.